Description:
System and method for reducing the power dissipation and energy requirements of high-performance microprocessors through the incremental allocation and deallocation of units of datapath resources
Background:
Modern, high-performance microprocessors use sophisticated instruction scheduling mechanisms and pipelines designed to reorder the startup and completion of instructions in a sequential instruction stream so as to achieve a high-level of processor performance. One common form of such mechanisms is a superscalar microprocessor that is capable of fetching, decoding, issuing, executing, completing and retiring more than one instruction within a single cycle of the clock signal used to synchronize activities at the lowest level in the microprocessor, which utilize a lot of energy from the system.
Technology Overview:
The present invention is a system and method for reducing the power dissipation and energy requirements of high-performance microprocessors through the incremental allocation and deallocation of units of datapath resources like reorder buffers, physical registers, instruction queues and load-store queues. The allocation and deallocation decisions for these resources are made independently at run-time based on sampled estimates of the instantaneous resource needs of the program running on the microprocessor. Power and energy savings are achieved by shutting off resource units that are not needed for sustaining the performance requirements. Leakage energy and power as well as switching energy and power are reduced using the invention described.
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Intellectual Property Summary:
U.S. 7,219,249
U.S. 7,562,243
U.S. 8,321,712
U.S. 8,700,938