Mixed-size placement—the integration of large macro blocks and dense standard cells—is a persistent challenge in IC design. Current industry tools separate manual macro block placement from automated standard cell placement, leading to bottlenecks, inconsistent results, and extended design cycles. It is common for design teams to rely on human experts to find an initial location of macro blocks. Existing academic methods like simulated annealing or sequence pair representations work well for small floor-planning problems, but often lack scalability and robustness for real-world system-on-chip (SoC) complexity. There remains a critical need for a practical, automated solution that delivers optimized wire lengths, timing, and power consumption, that is reliable and predictable at scale.
The invention introduces Stored Hierarchical Abstract Relative Placement (SHARP), a method that leverages the recursive bisection cut tree to guide a Hierarchical Hybrid Legalization process. This approach incrementally legalizes subtrees, dynamically adjusts aspect ratios, and integrates macro and standard cell placements. Pareto optimization and dynamic programming control solution complexity, while whitespace management, buffer insertion, and neural network refinements improve routability and timing closure. The result is an automated, scalable mixed-size placement solution that combines the predictability of manual flows with the efficiency of advanced partitioning.
• Combines placement of large and small circuit components in one step, reducing manual effort and design delays.
• Reuses key data from early design stages to improve layout quality and consistency.
• Optimizes performance and cost without overwhelming the system with too many design options.
• Identifies and solves congestion issues early, leading to smoother and more reliable routing.
• Increases predictability and speeds up design cycles compared to traditional automated tools.
• Supports next-generation chip designs, including 3D integration and IP reuse, for greater scalability and flexibility.
• United States – 63/459,239, Provisional, filed 04/13/2023, Converted
• United States – 18/634,860, Utility, filed 04/12/2024, Published as US-20240354481 A1
Algorithm-level validation with benchmarking on academic and industrial datasets.
This technology is available for licensing.
Applicable to leading EDA vendors and semiconductor design houses seeking scalable, automated placement engines to improve chip performance, timing closure, and design iteration speed.
Benchmark results and integration framework details available upon request.